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Overview
Core3S500E is an FPGA core board that features an XC3S500E device onboard, supports further expansion.
onboard 1pcs XCF04S
integrated FPGA basic circuit, such as clock circuit
onboard nCONFIG button, RESET button, 4 x LEDs
all the I/O ports are accessible on the pin headers
onboard JTAG debugging/programming interface
2.0mm header pitch design, suitable for being plugged-in your application system
What's On Board
XC3S500E:the XILINX Spartan-3E FPGA device which features:
Operating Frequency: 50MHz
Operating Voltage: 1.15V¡«3.3V
Package: QFP208
I/Os: 116
LEs: 500K
RAM: 360kb
DCMs: 4
Debugging/Programming: supports JTAG
AMS1117-3.3, 3.3V voltage regulator
AMS1117-2.5, 2.5V voltage regulator
AMS1117-1.2, 1.2V voltage regulator
XCF04S, onboard serial FLASH memory, for storing code
Power indicator
LEDs
FPGA initialization indicator
Reset button
nCONFIG button: for re-configuring the FPGA chip, the equivalent of power reseting
50M active crystal oscillator
JTAG interface: for debugging/programming
FPGA pins expander, VCC, GND and all the I/O ports are accessible on expansion connectors for further expansion
Weight:0.044 kg
Package List
Package Contains
Core3S500E core board x 1
Overview
Core3S500E is an FPGA core board that features an XC3S500E device onboard, supports further expansion.
onboard 1pcs XCF04S
integrated FPGA basic circuit, such as clock circuit
onboard nCONFIG button, RESET button, 4 x LEDs
all the I/O ports are accessible on the pin headers
onboard JTAG debugging/programming interface
2.0mm header pitch design, suitable for being plugged-in your application system
What's On Board
XC3S500E:the XILINX Spartan-3E FPGA device which features:
Operating Frequency: 50MHz
Operating Voltage: 1.15V¡«3.3V
Package: QFP208
I/Os: 116
LEs: 500K
RAM: 360kb
DCMs: 4
Debugging/Programming: supports JTAG
AMS1117-3.3, 3.3V voltage regulator
AMS1117-2.5, 2.5V voltage regulator
AMS1117-1.2, 1.2V voltage regulator
XCF04S, onboard serial FLASH memory, for storing code
Power indicator
LEDs
FPGA initialization indicator
Reset button
nCONFIG button: for re-configuring the FPGA chip, the equivalent of power reseting
50M active crystal oscillator
JTAG interface: for debugging/programming
FPGA pins expander, VCC, GND and all the I/O ports are accessible on expansion connectors for further expansion
Weight:0.044 kg
Package List
Package Contains
Core3S500E core board x 1
RETURNS POLICY
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